A flash ADC resolves an analog signal level to a digital number by comparing the analog signal at an instant in time to a set of thresholds. This comparison is performed by a set of analog samplers, which are also called clocked comparators.
The clocked comparator introduces a timing offset to the desired sampling instant, in addition to other imperfections. Timing errors in an ADC introduce distortion in the resolved digital signal and therefore degrade the ADC's signal to noise and distortion ratio (SNDR). In addition, clocked comparators may include threshold offset errors, which contribute to the overall noise and distortion of the ADC.
Sampler timing offsets may vary in a number of manners, such as:                differences between samplers;        differences between dies; and        differences between temperatures, processes, power supply voltages, which appear over time.        
A method for calibrating a sampler by introducing special test signals, known as “foreground calibration”, introduces a time when the ADC is not resolving the true input signal, and this is not acceptable for some applications.
Another existing method for calibrating samplers is by using special circuitry, such as Digital to Analog Converters. This solution, however, is expensive in terms of die area and power dissipation.
An alternative method is a onetime calibration (e.g., at power-up) where the calibration scheme does not interfere with the transmission scheme once the latter has begun. This method however is not optimal, since the calibration will degrade over time, which entails SNDR degradation over time, when the errors themselves change over time, due to the fact that temperature or other conditions change.
It would be advantageous to be able to remove ADC sampler timing offsets without interfering normal data transmission, while maintaining calibration throughout the entire transmission scheme, using an economical system.
It is therefore an object of the present invention to provide a method for calibrating ADC samplers and removing ADC sampler timing offsets, without interfering data transmission, while maintaining calibration through the entire transmission scheme using an economical system.
Other objects and advantages of this invention will become apparent as the description proceeds.